Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation
نویسندگان
چکیده
A logic style known as Phased Logic(PL) is applied to arithmetic circuits. Phased logic is a dual-rail LEDR logic style that allows automatic translation from a clocked netlist to a self-timed implementation. Bit level dataflow, early evaluation and automatic filtering of transient computations within PL circuits can lead to both increased performance and higher energy efficiency than the original clocked netlist. performance decrease but is 2X more energy efficient than the clocked counterpart.
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